Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Each row of the SRAM cells is connected to a word-line, which determines whether an SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of complementary bit-lines), which is used for storing a bit read into, or read from, the SRAM cell.
When integrated on system-on-chip (SOC) applications, the conventional SRAM cells face the increasing demanding requirement of reducing power consumption and increasing speed. However, in conventional 6T memories, the reduction of power consumption requires the operation voltage to be reduced. This results in a cell stability concern, which is caused by reduced Vcc_min, and hence reduced static noise margin (SNM).
To solve these problems, 8T SRAM cells have been explored. FIG. 1 illustrates a conventional 8T dual-port transistor, which includes a latch including PMOS transistor 2 110 and 112 and NMOS transistors 114 and 116. Pass-gate transistors 118 and 120 are controlled by write word-line WWL and act as write-port pass-gate transistors. Write-lines WBL and WBLB are used for writing data into the SRAM cell. Transistors 122 and 124 form the read-port of the SRAM cell, wherein pass-gate transistor 124 is controlled by read word-line RWL. Read-line RBL is used for reading data from the SRAM cell.
The 8T SRAM cell as shown in FIG. 1 is well suited for use in the case the multiplexing ratio (indicating how many columns share a multiplexer) is equal to 1. In this case, no multiplexing of columns is performed, and the 8T SRAM cell may have reduced static noise margin (SNM) and low Vcc_min without affecting the stability of the 8T SRAM cell. However, if the multiplexing ratio is greater than 1, and hence more than one column shares a multiplexer, the 8T SRAM cell has to trade off between write-read margin (WRM) and SNM, and the reduction of Vcc_min is limited.
Conventionally, to solve the possible 8T SRAM cell instability problem caused by reduced Vcc_min in dummy read operations, write-back technologies have been used, in which the values stored in the SRAM cells experiencing dummy read are read from and written back into the cells to ensure the stability of the stored value. However, this requires additional circuits, and the chip area penalty is high.